Currently, error detection in integrated circuits, e.g., programmable ICs such as field programmable gate arrays (FPGAs), require scanning to be performed from beginning to end (e.g., beginning at frame zero at the left and scanning to the right until the row ends) and then from one row to the next row in a sequential order. This method of error detection assumes that all logic within an IC is of equal importance.
As the amount of logic and the sizes of ICs grow, the time for scanning may rise into milliseconds or seconds. As a result, error detection and scanning using current methods can be very time consuming given the ever growing size of ICs.